1. Field
Example embodiments relate to a semiconductor memory device, for example, to a read data path circuit for use in a semiconductor memory device, such as a dynamic random access memory.
2. Description of the Related Art
In general, the semiconductor memory device, e.g., a dynamic random access memory, is increasingly operating at relatively higher speeds and becoming relatively more integrated due to user requirements. A dynamic random access memory device including one access transistor and one storage capacitor as a unit memory cell is generally employed as a main memory of an electronic system.
As illustrated in FIG. 1, a dynamic random access memory device 10 (hereinafter, referred to as ‘DRAM’) employed in a conventional data processing system is coupled to a micro processing unit 2 through a system bus B1 and functions as a main memory. For example, the micro processing unit 2 of the data processing system is coupled to a flash memory 4 through a system bus B5, and controls a drive unit 6 through a control bus B2 by performing a processing operation determined by a program stored in the flash memory 4. In controlling the drive unit 6, the micro processing unit 2 may perform a data access operation of writing data to a memory cell of the DRAM 10 and reading the written data from the memory cell, in order to perform the processing operation.
In the read operation of DRAM 10, data stored in the memory cell is sensed and amplified on a bit line pair by a bit line sense amplifier (hereinafter, referred to as “BLSA”), and then is transferred to a local input/output line pair when a column selection line (hereinafter, referred to as ‘CSL’) is activated. In an example of a method to transfer bit line data to the local input/output line pair, a precharge operation for the local input/output line pair may be performed and a potential difference may develop.
In this case, before the CSL is activated, the local input/output line pair is precharged to a given voltage level. At this time, when the CSL is activated, the precharged-charge escapes from one line of the local input/output line pair to one bit line of the bit line pair. Accordingly, a potential difference between a complementary local input/output line and a local input/output line constituting the local input/output line pair is developed, and an amplitude of the potential difference may increase as time lapses.
In a read data path circuit of DRAM performing an operation of applying data provided from the memory cell to an output buffer in a read operation and in employing the scheme of precharging the local input/output line, a bit line disturbance may occur, thus a measurement thereto may be required.